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<ul>
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
<ul>
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
</ul>
</li>
<li><a href="#timing" style=" font-size: 16px;">Timing</a>
<ul>
<li><a href="#clock" style=" font-size: 14px;">Clock Summary</a></li>
<li><a href="#performance" style=" font-size: 14px;">Max Frequency Summary</a></li>
<li><a href="#detail timing" style=" font-size: 14px;">Detail Timing Paths Informations</a></li>
</ul>
</li>
</ul>
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<div id="content">
<h1><a name="about">Synthesis Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>GowinSynthesis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>F:\TangPrimer-25K-example\hdmi\svo\src\gowin_pll\gowin_pll.v<br>
F:\TangPrimer-25K-example\hdmi\svo\src\hdmi\svo_defines.vh<br>
F:\TangPrimer-25K-example\hdmi\svo\src\hdmi\svo_enc.v<br>
F:\TangPrimer-25K-example\hdmi\svo\src\hdmi\svo_openldi.v<br>
F:\TangPrimer-25K-example\hdmi\svo\src\hdmi\svo_tcard.v<br>
F:\TangPrimer-25K-example\hdmi\svo\src\hdmi\svo_term.v<br>
F:\TangPrimer-25K-example\hdmi\svo\src\hdmi\svo_tmds.v<br>
F:\TangPrimer-25K-example\hdmi\svo\src\hdmi\svo_utils.v<br>
F:\TangPrimer-25K-example\hdmi\svo\src\hdmi\svo_vdma.v<br>
F:\TangPrimer-25K-example\hdmi\svo\src\svo_hdmi.v<br>
F:\TangPrimer-25K-example\hdmi\svo\src\top.v<br>
F:\TangPrimer-25K-example\hdmi\svo\src\gowin_clkdiv\gowin_clkdiv.v<br>
F:\TangPrimer-25K-example\hdmi\svo\src\hdmi\svo_pong.v<br>
</td>
</tr>
<tr>
<td class="label">GowinSynthesis Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Version</td>
<td>V1.9.9 Beta-3</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW5A-LV25MG121NES</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW5A-25</td>
</tr>
<tr>
<td class="label">Device Version</td>
<td>A</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Thu Aug 31 10:32:58 2023
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.</td>
</tr>
</table>
<h1><a name="summary">Synthesis Details</a></h1>
<table class="summary_table">
<tr>
<td class="label">Top Level Module</td>
<td>top</td>
</tr>
<tr>
<td class="label">Synthesis Process</td>
<td>Running parser:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 443.801MB<br/>Running netlist conversion:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 0: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.187s, Peak memory usage = 443.801MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 1: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.105s, Peak memory usage = 443.801MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 2: CPU time = 0h 0m 0.359s, Elapsed time = 0h 0m 0.331s, Peak memory usage = 443.801MB<br/>Running inference:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 0: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.135s, Peak memory usage = 443.801MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.037s, Peak memory usage = 443.801MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.044s, Peak memory usage = 443.801MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 3: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.068s, Peak memory usage = 443.801MB<br/>Running technical mapping:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 0: CPU time = 0h 0m 0.515s, Elapsed time = 0h 0m 0.512s, Peak memory usage = 443.801MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 1: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.078s, Peak memory usage = 443.801MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.058s, Peak memory usage = 443.801MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 3: CPU time = 0h 0m 24s, Elapsed time = 0h 0m 24s, Peak memory usage = 443.801MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 4: CPU time = 0h 0m 0.546s, Elapsed time = 0h 0m 0.536s, Peak memory usage = 443.801MB<br/>Generate output files:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.288s, Peak memory usage = 443.801MB<br/></td>
</tr>
<tr>
<td class="label">Total Time and Memory Usage</td>
<td>CPU time = 0h 0m 27s, Elapsed time = 0h 0m 27s, Peak memory usage = 443.801MB</td>
</tr>
</table>
<h1><a name="resource">Resource</a></h1>
<h2><a name="usage">Resource Usage Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
</tr>
<tr>
<td class="label"><b>I/O Port </b></td>
<td>27</td>
</tr>
<tr>
<td class="label"><b>I/O Buf </b></td>
<td>15</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspIBUF</td>
<td>2</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspOBUF</td>
<td>1</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspELVDS_OBUF</td>
<td>12</td>
</tr>
<tr>
<td class="label"><b>Register </b></td>
<td>1435</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFSE</td>
<td>6</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFRE</td>
<td>1395</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFCE</td>
<td>34</td>
</tr>
<tr>
<td class="label"><b>LUT </b></td>
<td>2515</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT2</td>
<td>296</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT3</td>
<td>1022</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT4</td>
<td>1197</td>
</tr>
<tr>
<td class="label"><b>ALU </b></td>
<td>360</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspALU</td>
<td>360</td>
</tr>
<tr>
<td class="label"><b>SSRAM </b></td>
<td>48</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspRAM16S4</td>
<td>27</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspRAM16SDP4</td>
<td>21</td>
</tr>
<tr>
<td class="label"><b>INV </b></td>
<td>16</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspINV</td>
<td>16</td>
</tr>
<tr>
<td class="label"><b>IOLOGIC </b></td>
<td>9</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspOSER10</td>
<td>9</td>
</tr>
<tr>
<td class="label"><b>BSRAM </b></td>
<td>3</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbsppROM</td>
<td>3</td>
</tr>
<tr>
<td class="label"><b>CLOCK </b></td>
<td>2</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspCLKDIV</td>
<td>1</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspPLLA</td>
<td>1</td>
</tr>
</table>
<h2><a name="utilization">Resource Utilization Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
<td><b>Utilization</b></td>
</tr>
<tr>
<td class="label">Logic</td>
<td>3179(2531 LUT, 360 ALU, 48 RAM16) / 23040</td>
<td>14%</td>
</tr>
<tr>
<td class="label">Register</td>
<td>1435 / 23280</td>
<td>7%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as Latch</td>
<td>0 / 23280</td>
<td>0%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as FF</td>
<td>1435 / 23280</td>
<td>7%</td>
</tr>
<tr>
<td class="label">BSRAM</td>
<td>3 / 56</td>
<td>6%</td>
</tr>
</table>
<h1><a name="timing">Timing</a></h1>
<h2><a name="clock">Clock Summary:</a></h2>
<table class="summary_table">
<tr>
<th>Clock Name</th>
<th>Type</th>
<th>Period</th>
<th>Frequency(MHz)</th>
<th>Rise</th>
<th>Fall</th>
<th>Source</th>
<th>Master</th>
<th>Object</th>
</tr>
<tr>
<td>clk</td>
<td>Base</td>
<td>20.000</td>
<td>50.0</td>
<td>0.000</td>
<td>10.000</td>
<td> </td>
<td> </td>
<td>clk_ibuf/I </td>
</tr>
<tr>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk</td>
<td>Generated</td>
<td>1.176</td>
<td>850.0</td>
<td>0.000</td>
<td>0.588</td>
<td>clk_ibuf/I</td>
<td>clk</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0 </td>
</tr>
<tr>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
<td>Generated</td>
<td>5.882</td>
<td>170.0</td>
<td>0.000</td>
<td>2.941</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT </td>
</tr>
</table>
<h2><a name="performance">Max Frequency Summary:</a></h2>
<table class="summary_table">
<tr>
<th>No.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>clk</td>
<td>50.0(MHz)</td>
<td>389.0(MHz)</td>
<td>5</td>
<td>TOP</td>
</tr>
<tr>
<td>2</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
<td>170.0(MHz)</td>
<td>91.4(MHz)</td>
<td>18</td>
<td>TOP</td>
</tr>
</table>
<h2><a name="detail timing">Detail Timing Paths Information</a></h2>
<h3>Path&nbsp1</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-5.058</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>11.212</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.154</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_1/svo_enc/out_axis_tdata_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_1/svo_tmds_2/cnt_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.152</td>
<td>0.152</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.332</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_enc/out_axis_tdata_0_s0/CLK</td>
</tr>
<tr>
<td>0.700</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>11</td>
<td>svo_hdmi_inst_1/svo_enc/out_axis_tdata_0_s0/Q</td>
</tr>
<tr>
<td>0.880</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n407_s3/I0</td>
</tr>
<tr>
<td>1.385</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n407_s3/F</td>
</tr>
<tr>
<td>1.565</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n88_s8/I1</td>
</tr>
<tr>
<td>2.060</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n88_s8/F</td>
</tr>
<tr>
<td>2.240</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n88_s4/I3</td>
</tr>
<tr>
<td>2.492</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n88_s4/F</td>
</tr>
<tr>
<td>2.672</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n88_s1/I1</td>
</tr>
<tr>
<td>3.168</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n88_s1/F</td>
</tr>
<tr>
<td>3.348</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n88_s0/I0</td>
</tr>
<tr>
<td>3.853</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>29</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n88_s0/F</td>
</tr>
<tr>
<td>4.033</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n146_s11/I0</td>
</tr>
<tr>
<td>4.538</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n146_s11/F</td>
</tr>
<tr>
<td>4.718</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n146_s10/I0</td>
</tr>
<tr>
<td>5.224</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n146_s10/F</td>
</tr>
<tr>
<td>5.404</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n176_s13/I0</td>
</tr>
<tr>
<td>5.909</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n176_s13/F</td>
</tr>
<tr>
<td>6.089</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n245_s/I1</td>
</tr>
<tr>
<td>6.629</td>
<td>0.540</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n245_s/COUT</td>
</tr>
<tr>
<td>6.629</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n326_s/CIN</td>
</tr>
<tr>
<td>6.863</td>
<td>0.234</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n326_s/SUM</td>
</tr>
<tr>
<td>7.043</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n326_s0/I0</td>
</tr>
<tr>
<td>7.577</td>
<td>0.534</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n326_s0/COUT</td>
</tr>
<tr>
<td>7.577</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n325_s0/CIN</td>
</tr>
<tr>
<td>7.625</td>
<td>0.048</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n325_s0/COUT</td>
</tr>
<tr>
<td>7.625</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n324_s0/CIN</td>
</tr>
<tr>
<td>7.859</td>
<td>0.234</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n324_s0/SUM</td>
</tr>
<tr>
<td>8.039</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n378_s5/I0</td>
</tr>
<tr>
<td>8.544</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n378_s5/F</td>
</tr>
<tr>
<td>8.724</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n377_s5/I3</td>
</tr>
<tr>
<td>8.976</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n377_s5/F</td>
</tr>
<tr>
<td>9.156</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n377_s3/I0</td>
</tr>
<tr>
<td>9.661</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n377_s3/F</td>
</tr>
<tr>
<td>9.841</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n377_s1/I0</td>
</tr>
<tr>
<td>10.346</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n377_s1/F</td>
</tr>
<tr>
<td>10.526</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n377_s0/I0</td>
</tr>
<tr>
<td>11.032</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n377_s0/F</td>
</tr>
<tr>
<td>11.212</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_2/cnt_7_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>6.035</td>
<td>0.152</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>6.215</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_2/cnt_7_s0/CLK</td>
</tr>
<tr>
<td>6.154</td>
<td>-0.061</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_2/cnt_7_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>5.882</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>18</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.180, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 7.632, 70.152%; route: 2.880, 26.473%; tC2Q: 0.367, 3.375%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.180, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp2</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.996</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>11.149</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.154</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_1/svo_enc/out_axis_tdata_8_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_1/svo_tmds_1/cnt_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.152</td>
<td>0.152</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.332</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_enc/out_axis_tdata_8_s0/CLK</td>
</tr>
<tr>
<td>0.700</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>14</td>
<td>svo_hdmi_inst_1/svo_enc/out_axis_tdata_8_s0/Q</td>
</tr>
<tr>
<td>0.880</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_1/n407_s3/I0</td>
</tr>
<tr>
<td>1.385</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>10</td>
<td>svo_hdmi_inst_1/svo_tmds_1/n407_s3/F</td>
</tr>
<tr>
<td>1.565</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_1/n175_s19/I1</td>
</tr>
<tr>
<td>2.060</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>svo_hdmi_inst_1/svo_tmds_1/n175_s19/F</td>
</tr>
<tr>
<td>2.240</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_1/n88_s3/I3</td>
</tr>
<tr>
<td>2.492</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>svo_hdmi_inst_1/svo_tmds_1/n88_s3/F</td>
</tr>
<tr>
<td>2.672</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_1/n88_s1/I0</td>
</tr>
<tr>
<td>3.178</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>svo_hdmi_inst_1/svo_tmds_1/n88_s1/F</td>
</tr>
<tr>
<td>3.358</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_1/n146_s17/I0</td>
</tr>
<tr>
<td>3.863</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>svo_hdmi_inst_1/svo_tmds_1/n146_s17/F</td>
</tr>
<tr>
<td>4.043</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_1/n146_s13/I1</td>
</tr>
<tr>
<td>4.538</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>svo_hdmi_inst_1/svo_tmds_1/n146_s13/F</td>
</tr>
<tr>
<td>4.718</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_1/n146_s10/I2</td>
</tr>
<tr>
<td>5.161</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>svo_hdmi_inst_1/svo_tmds_1/n146_s10/F</td>
</tr>
<tr>
<td>5.341</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_1/n176_s13/I0</td>
</tr>
<tr>
<td>5.846</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>svo_hdmi_inst_1/svo_tmds_1/n176_s13/F</td>
</tr>
<tr>
<td>6.026</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>svo_hdmi_inst_1/svo_tmds_1/n245_s/I1</td>
</tr>
<tr>
<td>6.566</td>
<td>0.540</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_1/n245_s/COUT</td>
</tr>
<tr>
<td>6.566</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>svo_hdmi_inst_1/svo_tmds_1/n326_s/CIN</td>
</tr>
<tr>
<td>6.800</td>
<td>0.234</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_1/n326_s/SUM</td>
</tr>
<tr>
<td>6.980</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>svo_hdmi_inst_1/svo_tmds_1/n326_s0/I0</td>
</tr>
<tr>
<td>7.514</td>
<td>0.534</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_1/n326_s0/COUT</td>
</tr>
<tr>
<td>7.514</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>svo_hdmi_inst_1/svo_tmds_1/n325_s0/CIN</td>
</tr>
<tr>
<td>7.562</td>
<td>0.048</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_1/n325_s0/COUT</td>
</tr>
<tr>
<td>7.562</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>svo_hdmi_inst_1/svo_tmds_1/n324_s0/CIN</td>
</tr>
<tr>
<td>7.796</td>
<td>0.234</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>svo_hdmi_inst_1/svo_tmds_1/n324_s0/SUM</td>
</tr>
<tr>
<td>7.976</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_1/n378_s5/I0</td>
</tr>
<tr>
<td>8.482</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>svo_hdmi_inst_1/svo_tmds_1/n378_s5/F</td>
</tr>
<tr>
<td>8.662</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_1/n377_s5/I3</td>
</tr>
<tr>
<td>8.914</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_1/n377_s5/F</td>
</tr>
<tr>
<td>9.094</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_1/n377_s3/I0</td>
</tr>
<tr>
<td>9.599</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_1/n377_s3/F</td>
</tr>
<tr>
<td>9.779</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_1/n377_s1/I0</td>
</tr>
<tr>
<td>10.284</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_1/n377_s1/F</td>
</tr>
<tr>
<td>10.464</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_1/n377_s0/I0</td>
</tr>
<tr>
<td>10.969</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_1/n377_s0/F</td>
</tr>
<tr>
<td>11.149</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_1/cnt_7_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>6.035</td>
<td>0.152</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>6.215</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_1/cnt_7_s0/CLK</td>
</tr>
<tr>
<td>6.154</td>
<td>-0.061</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>svo_hdmi_inst_1/svo_tmds_1/cnt_7_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>5.882</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>18</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.180, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 7.570, 69.980%; route: 2.880, 26.625%; tC2Q: 0.367, 3.395%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.180, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp3</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.943</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>11.096</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.154</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_2/svo_enc/out_axis_tdata_16_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_2/svo_tmds_0/cnt_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.152</td>
<td>0.152</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.332</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_2/svo_enc/out_axis_tdata_16_s0/CLK</td>
</tr>
<tr>
<td>0.700</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>12</td>
<td>svo_hdmi_inst_2/svo_enc/out_axis_tdata_16_s0/Q</td>
</tr>
<tr>
<td>0.880</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n406_s3/I0</td>
</tr>
<tr>
<td>1.385</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n406_s3/F</td>
</tr>
<tr>
<td>1.565</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n406_s5/I0</td>
</tr>
<tr>
<td>2.070</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n406_s5/F</td>
</tr>
<tr>
<td>2.250</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n88_s4/I3</td>
</tr>
<tr>
<td>2.502</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n88_s4/F</td>
</tr>
<tr>
<td>2.682</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n88_s2/I2</td>
</tr>
<tr>
<td>3.125</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n88_s2/F</td>
</tr>
<tr>
<td>3.305</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n88_s0/I2</td>
</tr>
<tr>
<td>3.748</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>32</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n88_s0/F</td>
</tr>
<tr>
<td>3.928</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n175_s15/I0</td>
</tr>
<tr>
<td>4.433</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n175_s15/F</td>
</tr>
<tr>
<td>4.613</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n175_s14/I0</td>
</tr>
<tr>
<td>5.118</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n175_s14/F</td>
</tr>
<tr>
<td>5.298</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n176_s13/I1</td>
</tr>
<tr>
<td>5.794</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n176_s13/F</td>
</tr>
<tr>
<td>5.974</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n245_s/I1</td>
</tr>
<tr>
<td>6.514</td>
<td>0.540</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n245_s/COUT</td>
</tr>
<tr>
<td>6.514</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n326_s/CIN</td>
</tr>
<tr>
<td>6.748</td>
<td>0.234</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n326_s/SUM</td>
</tr>
<tr>
<td>6.928</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n326_s0/I0</td>
</tr>
<tr>
<td>7.462</td>
<td>0.534</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n326_s0/COUT</td>
</tr>
<tr>
<td>7.462</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n325_s0/CIN</td>
</tr>
<tr>
<td>7.510</td>
<td>0.048</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n325_s0/COUT</td>
</tr>
<tr>
<td>7.510</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n324_s0/CIN</td>
</tr>
<tr>
<td>7.744</td>
<td>0.234</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n324_s0/SUM</td>
</tr>
<tr>
<td>7.924</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n378_s5/I0</td>
</tr>
<tr>
<td>8.429</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n378_s5/F</td>
</tr>
<tr>
<td>8.609</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n377_s5/I3</td>
</tr>
<tr>
<td>8.861</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n377_s5/F</td>
</tr>
<tr>
<td>9.041</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n377_s3/I0</td>
</tr>
<tr>
<td>9.546</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n377_s3/F</td>
</tr>
<tr>
<td>9.726</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n377_s1/I0</td>
</tr>
<tr>
<td>10.231</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n377_s1/F</td>
</tr>
<tr>
<td>10.411</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n377_s0/I0</td>
</tr>
<tr>
<td>10.916</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n377_s0/F</td>
</tr>
<tr>
<td>11.096</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_2/svo_tmds_0/cnt_7_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>6.035</td>
<td>0.152</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>6.215</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_2/svo_tmds_0/cnt_7_s0/CLK</td>
</tr>
<tr>
<td>6.154</td>
<td>-0.061</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>svo_hdmi_inst_2/svo_tmds_0/cnt_7_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>5.882</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>18</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.180, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 7.517, 69.833%; route: 2.880, 26.756%; tC2Q: 0.367, 3.411%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.180, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp4</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.742</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.896</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.154</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_0/svo_enc/out_axis_tdata_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_0/svo_tmds_2/cnt_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.152</td>
<td>0.152</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.332</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_enc/out_axis_tdata_4_s0/CLK</td>
</tr>
<tr>
<td>0.700</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>9</td>
<td>svo_hdmi_inst_0/svo_enc/out_axis_tdata_4_s0/Q</td>
</tr>
<tr>
<td>0.880</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n146_s18/I0</td>
</tr>
<tr>
<td>1.385</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n146_s18/F</td>
</tr>
<tr>
<td>1.565</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n88_s4/I1</td>
</tr>
<tr>
<td>2.060</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n88_s4/F</td>
</tr>
<tr>
<td>2.240</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n88_s2/I2</td>
</tr>
<tr>
<td>2.683</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n88_s2/F</td>
</tr>
<tr>
<td>2.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n88_s3/I3</td>
</tr>
<tr>
<td>3.115</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n88_s3/F</td>
</tr>
<tr>
<td>3.295</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n88_s0/I3</td>
</tr>
<tr>
<td>3.547</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>30</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n88_s0/F</td>
</tr>
<tr>
<td>3.727</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n146_s12/I0</td>
</tr>
<tr>
<td>4.232</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n146_s12/F</td>
</tr>
<tr>
<td>4.412</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n146_s10/I1</td>
</tr>
<tr>
<td>4.908</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n146_s10/F</td>
</tr>
<tr>
<td>5.088</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n176_s13/I0</td>
</tr>
<tr>
<td>5.593</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n176_s13/F</td>
</tr>
<tr>
<td>5.773</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n245_s/I1</td>
</tr>
<tr>
<td>6.313</td>
<td>0.540</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n245_s/COUT</td>
</tr>
<tr>
<td>6.313</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n326_s/CIN</td>
</tr>
<tr>
<td>6.547</td>
<td>0.234</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n326_s/SUM</td>
</tr>
<tr>
<td>6.727</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n326_s0/I0</td>
</tr>
<tr>
<td>7.261</td>
<td>0.534</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n326_s0/COUT</td>
</tr>
<tr>
<td>7.261</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n325_s0/CIN</td>
</tr>
<tr>
<td>7.309</td>
<td>0.048</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n325_s0/COUT</td>
</tr>
<tr>
<td>7.309</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n324_s0/CIN</td>
</tr>
<tr>
<td>7.543</td>
<td>0.234</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n324_s0/SUM</td>
</tr>
<tr>
<td>7.723</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n378_s5/I0</td>
</tr>
<tr>
<td>8.228</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n378_s5/F</td>
</tr>
<tr>
<td>8.408</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n377_s5/I3</td>
</tr>
<tr>
<td>8.660</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n377_s5/F</td>
</tr>
<tr>
<td>8.840</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n377_s3/I0</td>
</tr>
<tr>
<td>9.346</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n377_s3/F</td>
</tr>
<tr>
<td>9.526</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n377_s1/I0</td>
</tr>
<tr>
<td>10.031</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n377_s1/F</td>
</tr>
<tr>
<td>10.211</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n377_s0/I0</td>
</tr>
<tr>
<td>10.716</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n377_s0/F</td>
</tr>
<tr>
<td>10.896</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_2/cnt_7_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>6.035</td>
<td>0.152</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>6.215</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_2/cnt_7_s0/CLK</td>
</tr>
<tr>
<td>6.154</td>
<td>-0.061</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_2/cnt_7_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>5.882</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>18</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.180, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 7.316, 69.261%; route: 2.880, 27.263%; tC2Q: 0.367, 3.476%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.180, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp5</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.742</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.896</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.154</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_0/svo_enc/out_axis_tdata_12_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_0/svo_tmds_1/cnt_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.152</td>
<td>0.152</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.332</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_enc/out_axis_tdata_12_s0/CLK</td>
</tr>
<tr>
<td>0.700</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>10</td>
<td>svo_hdmi_inst_0/svo_enc/out_axis_tdata_12_s0/Q</td>
</tr>
<tr>
<td>0.880</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n146_s18/I0</td>
</tr>
<tr>
<td>1.385</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n146_s18/F</td>
</tr>
<tr>
<td>1.565</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n88_s4/I1</td>
</tr>
<tr>
<td>2.060</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n88_s4/F</td>
</tr>
<tr>
<td>2.240</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n88_s2/I2</td>
</tr>
<tr>
<td>2.683</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n88_s2/F</td>
</tr>
<tr>
<td>2.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n88_s3/I3</td>
</tr>
<tr>
<td>3.115</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n88_s3/F</td>
</tr>
<tr>
<td>3.295</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n88_s0/I3</td>
</tr>
<tr>
<td>3.547</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>30</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n88_s0/F</td>
</tr>
<tr>
<td>3.727</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n146_s12/I0</td>
</tr>
<tr>
<td>4.232</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n146_s12/F</td>
</tr>
<tr>
<td>4.412</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n146_s10/I1</td>
</tr>
<tr>
<td>4.908</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n146_s10/F</td>
</tr>
<tr>
<td>5.088</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n176_s13/I0</td>
</tr>
<tr>
<td>5.593</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n176_s13/F</td>
</tr>
<tr>
<td>5.773</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n245_s/I1</td>
</tr>
<tr>
<td>6.313</td>
<td>0.540</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n245_s/COUT</td>
</tr>
<tr>
<td>6.313</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n326_s/CIN</td>
</tr>
<tr>
<td>6.547</td>
<td>0.234</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n326_s/SUM</td>
</tr>
<tr>
<td>6.727</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n326_s0/I0</td>
</tr>
<tr>
<td>7.261</td>
<td>0.534</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n326_s0/COUT</td>
</tr>
<tr>
<td>7.261</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n325_s0/CIN</td>
</tr>
<tr>
<td>7.309</td>
<td>0.048</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n325_s0/COUT</td>
</tr>
<tr>
<td>7.309</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n324_s0/CIN</td>
</tr>
<tr>
<td>7.543</td>
<td>0.234</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n324_s0/SUM</td>
</tr>
<tr>
<td>7.723</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n378_s5/I0</td>
</tr>
<tr>
<td>8.228</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n378_s5/F</td>
</tr>
<tr>
<td>8.408</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n377_s5/I3</td>
</tr>
<tr>
<td>8.660</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n377_s5/F</td>
</tr>
<tr>
<td>8.840</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n377_s3/I0</td>
</tr>
<tr>
<td>9.346</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n377_s3/F</td>
</tr>
<tr>
<td>9.526</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n377_s1/I0</td>
</tr>
<tr>
<td>10.031</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n377_s1/F</td>
</tr>
<tr>
<td>10.211</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n377_s0/I0</td>
</tr>
<tr>
<td>10.716</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n377_s0/F</td>
</tr>
<tr>
<td>10.896</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_1/cnt_7_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>6.035</td>
<td>0.152</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>6.215</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_1/cnt_7_s0/CLK</td>
</tr>
<tr>
<td>6.154</td>
<td>-0.061</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>svo_hdmi_inst_0/svo_tmds_1/cnt_7_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>5.882</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>18</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.180, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 7.316, 69.261%; route: 2.880, 27.263%; tC2Q: 0.367, 3.476%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.180, 100.000%</td></tr>
</table>
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